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1 60v, 1a/2a peak, 1/2 bridge driver with 4v uvlo hip2103, hip2104 the hip2103 and hip2104 are half bridge drivers designed for applications using dc motors, three-phase brushless dc motors, or other similar loads. two inputs (hi and li) are provided to independently control the high side driver (ho) and the low side driver (lo). furthermore, the two inputs can be configured to enable/disable the device, thus lowering the number of connections to a microcontroller and lowering costs. the very low idd bias current in the sleep mode prevents battery drain when the device is not in use, thus eliminating the need for an external switch to disconnect the driver from the battery. a fail-safe mechanism is included to improve system reliability and to minimize the possibility of catastrophic bridge failures due to controller malfunction. internal logic prevents both outputs from turning on simultaneously when hi and li are both high simultaneously. dead-t ime is still required on the rising edge of the hi (or li) input when the li (or hi) input transitions low. integrated pull-down resistors on all of the inputs (li, hi, vden and vcen) reduces the need for external resistors. an active low resistance pull-down on the lo output ensures that the low side bridge fet remains off during the sleep mode or when vdd is below the undervoltage lockout (uvlo) threshold. the hip2104 has a 12v linear regulator and a 3.3v linear regulator with separate enable pins. the 12v regulator provides internal bias for vdd and the 3.3v regulator provides bias for an external microcontr oller (and/or other low voltage ics), thus eliminating the need for discrete ldos or dc/dc converters. the hip2103 is available in a 3x3mm, 8 ld tdfn package and the hip2104 is available in a 4x4mm, 12 ld dfn package. features ? 60v maximum bootstrap supply voltage ? 3.3v and 12v ldos with dedicated enable pins (hip2104) ? 5a sleep mode quiescent current ? 4v undervoltage lockout ? 3.3v or 5v cmos compatible inputs with hysteresis ? integrated bootstrap fet (replace s traditional boot strap diode) applications ? half bridge, full bridge and bldc motor drives (see figures 21, 22, 23) ?ups and inverters ? class-d amplifiers ? any switch mode power circuit requiring a half bridge driver related literature ? an1896 ?hip2103, hip2104 evaluation board user?s guide? ? an1899 ?hip2103, hip2104 3-phase, full or half bridge motor drive? figure 1. typical full bridge application f igure 2. hip2104 shutdown current vs v bat controller hip2104 vbat vcen vcc vdd hi li epad lo hs ho hb vden vss dc motor vbat vbat hi li lo hs ho hb vss hip2103 epad vdd vdd 3.5 4.0 4.5 5.0 5.5 i bat (a) 2.0 2.5 3.0 10 20 30 40 50 v bat (vdc) november 27, 2013 fn8276.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
hip2103, hip2104 2 fn8276.0 november 27, 2013 block diagram symbol glossary 3.3v ldo 1 msec delay 155c ot 12v ldo 1 msec delay vden vdd vcen 1 4v under voltage 20 us delay 20 us delay vdd hb sleep mode level shift 4v under voltage r s q ho lo hs vss vdd vbat logic bias hi li e p a d 100k 100 100k vcc vbat logic prevents shoot-through when li and hi are both high active pull-down keeps bridge fet off during uv, ot, or sleep 2104 2103 2104 2103 10 us delay time delay functional block with rising edge prop delay (as indicated by the rising arrow on the input) and minimal falling edge delay. 2104 2103 optional connections as indicated by part numbers hip2104 hip2103 2m 100k 100k boot fet see figures 3 and 4 for sleep mode timing details
hip2103, hip2104 3 fn8276.0 november 27, 2013 pin configurations hip2103 (8 ld 3x3 tdfn) top view hip2104 (12 ld 4x4 dfn) top view epad (vss) 1 2 3 4 8 7 6 5 vdd hi li vss hb ho hs lo epad (vss) 1 2 3 4 12 11 10 9 8 vden vcen vcc vdd hi vbat hb ho hs lo 6 5 li 7 vss pin descriptions hip2103 hip2104 symbol description 8 ld tdfn 12 ld dfn - 1 vden (hip2104 only) vdd enable input, 3.3v or 5v logic compatible, v bat tolerant. vdd output is turned on after 1ms debouncing period. - 2 vcen (hip2104 only) vcc enable input, 3.3v or 5v logic compatible. v bat tolerant. vcc output is turned on after 1ms debouncing period. - 3 vcc (hip2104 only) 3.3v output voltage of linear regulator, 75ma. enabled by vcen. 1 4 vdd (hip2103) input voltage 14v max. (hip2104) 0utput voltage of linear regulato r, 12v nominal, 75ma. enabled by vden. 25hi h igh side input, 3.3v or 5v logic compatible. (hi -> ho). 36li l ow side i nput, 3.3v or 5v logic compatible. (li -> lo). 47vss s ignal ground. 58lo l ow side driver o utput. (li ->lo). 69hs h igh side fet s ource connection (low side boot capacitor connection). 710ho h igh side driver o utput. (hi -> ho) 811hb h igh side b oot capacitor. - 12 vbat (hip2104 only) positive battery (bridge voltage) connection. ep ep epad exposed pad, must be connected to signal ground.
hip2103, hip2104 4 fn8276.0 november 27, 2013 ordering information part number (notes 1, 2, 3, 4) part marking uvlo (v) vcc regulator (v) vdd regulator (v) package (pb-free) pkg. dwg. # hip2103frtaaz dzbf 4.0 n/a n/a 8 ld 3x3 tdfn l8.3x3a hip2104fraanz 2104an 4.0 3.3 12 12 ld 4x4 dfn l12.4x4a hip2103_4demo1z hip2103, hip2104 3-phase, full, or half bridge motor drive demonstration board hip2103_4mbeval1z hip2103, hip2104 evaluation board notes: 1. add ?-t*?, suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for hip2103 , hip2104 . for more information on msl, please see technical brief tb363 4. all part numbers are rated -40c to +125c for th e recommended operating junction temperature range.
hip2103, hip2104 5 fn8276.0 november 27, 2013 absolute maximum ratings (note 5) thermal information supply voltage v dd (hip2103 only) . . . . . . . . . . . . . . . . . . . . . . -0.3v to 16v bridge supply voltage v bat (hip2104 only) . . . . . . . . . . . . . . . -0.3v to 60v high side bias voltage (v hb - v hs) (note 10). . . . . . . . . . . . . . . -0.3v to 16v logic inputs vcen, vden (hip2104 only) . . . . . . . . . . - 0.3v to v bat + 0.3v logic inputs li, hi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to v dd + 0.3v output voltage lo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to v dd + 0.3v output voltage ho . . . . . . . . . . . . . . . . . . . . . . . . . . v hs - 0.3v to v hb + 0.3v voltage on hs (note 9, 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10v to 60v voltage on hb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v hs - 0.3v to 66v average current in boot diode (note 6). . . . . . . . . . . . . . . . . . . . . . . 100ma maximum boot cap value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10f average output current in ho and lo (note 6) . . . . . . . . . . . . . . . . 200ma esd ratings human body model class 2 (tested per jesd22-a114e) . . . . . . 2000v charged device model class iv . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000v latch-up (tested per jesd-78b; class 2, level a) all pins. . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 8 ld dfn package (notes 7, 8). . . . . . . . . . 46 7 12 ld tdfn package (notes 7, 8) . . . . . . . 44 7 max power dissipation at +25c in free air 8 ld dfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3w 12 ld tdfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2w max power dissipation at +25c on copper plane 8 ld dfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3w 12 ld tdfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3w storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c maximum operating junction temperature range. . . . . . -40c to +150c nominal over temperature shut-down . . . . . . . . . . . . . . . . . . . . . . .+155c over temperature shut-down range . . . . . . . . . . . . . . . +145c to +165c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions (note 5) junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c supply voltage, v bat (hip2104 only) (note 11). . . . . . . . . . . . . 5.0v to 50v supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 14v high side bias voltage (v hb - v hs) (note 10) . . . . . . . . . . . . . . -0.3v to 14v voltage on hs, continuous, v hs (note 9, 10) . . . . . . . . . . . . . . .-10v to 50v voltage on hb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v hs - 0.3v to 60v logic inputs vcen, vden (hip2104 only). . . . . . . . . . . . . . . . . . . .0v to v bat output voltage (lo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd to v dd output voltage (ho) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v hs to v hb average output current in ho and lo (note 6) . . . . . . . . . . . . 0 to 150ma caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. all voltages are referenced to vss unless otherwise specified. 6. the average output current, when driving a power mosf et or similar capacitive load, is the average of the rectified output current. the peak output currents of this driver are self limiting by trans conductance or r ds(on) and do not required any external comp onents to minimize the peaks. if the output is driving a non-capacitive load, such as an led, the maximum output current must be limited by external means to less t han the specified recommended rectified average output current. 7. ja is measured in free air with the componen t mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 8. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 9. the the maximum value of v hs must be limited so that v hb does not exceed 60v. 10. the -10v limit for v hs has no time duration restrictions as far as the hs pin is concer ned however, be aware that if the duration of the negative volt age is significant with respect to the time constant to charge the boot capacitor (across hb and hs) the voltage on the boot capaci tor can charge as high as v dd - (-v hs ) = (v dd +v hs ) potentially violating the voltage rating for (v hb - v hs). 11. when v bat < ~13v, the output of vdd will sag. the 5v minimum specified for v bat is the minimum level for which the uvlo will not activate. dc electrical specifications v dd = v hb = 12v (for hip2103), v ss = v hs = 0v, v bat = 18v (for hip2104), li = hi = 0v. no load on ho and lo unless otherwise specified. boldface limits apply over the operating junction temperature range, -40c to +125c . parameters symbol test conditions t j = +25c t j = -40c to +125c units min typ max min (note 12) max (note 12) linear bias supplies (hip2104 only) v dd output voltage over rated line, load, and temperature v dd12 nominal v dd = 12v -2.5 +2.1 +4.8 - 5% + 5% % v dd rated output current i ddr 75 ma v dd output current limit (brick wall) i dd12 83 151 237 80 245 ma
hip2103, hip2104 6 fn8276.0 november 27, 2013 v dd drop output voltage (figure 7) vddout load = 75ma 0.06 0.7 v v cc output voltage over rated line, load, and temperature v cc3.3 nominal v cc = 3.3v -3.9 +1.8 +4.3 - 5% + 5% % v cc rated output current i cdr 75 ma v cc output current limit (brick wall) i cc 83 149 237 80 245 ma v cc drop output voltage (figure 8) vcdout load = 75ma 0.5 0.9 v bias currents v dd sleep mode current (hip2103) i dds hi = li = 1, after 10 to 30s delay 9.4 20 a v bat shutdown current (hip2104) i ddsbatt vcen = vden = 0, after 10 to 30s delay, v bat = 50v 4.8 15 a v bat (hip2104) or vdd (hip2103) operating current i ddo20 f = 20khz, hi = li = 50% square wave v dd = 12v for hip2103 832 1040 a i ddo10 f = 10khz, hi = li = 50% square wave v dd = 12v for hip2103 661 825 a hb to hs quiescent current ihbq hi = 1, lo = 0, v hs = 0v, v hb = 12v 135 160 a hb to hs operating current i hbs20k li = 0, hi = 50% square wave 20khz, v hs = 0v, v hb = 12v 206 245 a i hbs10k li = 0, hi = 50% square wave 10khz, v hs = 0v, v hb = 12v 167 193 a hb to v ss operating current i hb20k li = 0, hi = 50% square wave 20khz, v hb = 60v, v hs = 50v 201 240 a i hb10k li = 0, hi = 50% square wave 10khz, v hb = 60v, v hs = 50v 164 190 a hb to v ss quiescent current i hbq li = hi = 0v; v hb = 60v, v hs = 50v 120 145 a hs to v ss current, sleep mode i hbs li = hi = 1; hb open, v hs = 50v 0.03 +1 a input pins low level input voltage threshold v il v dd = 12v 1.44 1.18 1.63 v high level input voltage threshold v ih 2.06 1.73 2.4 v input voltage hysteresis v hys 0.62 0.48 0.85 v low level input voltage threshold v il v dd = 5v 1.13 0.9 1.25 v high level input voltage threshold v ih 1.63 1.38 1.84 v input voltage hysteresis v hys 0.50 0.36 0.63 v input pull-down r i 100 80 130 k ? dc electrical specifications v dd = v hb = 12v (for hip2103), v ss = v hs = 0v, v bat = 18v (for hip2104), li = hi = 0v. no load on ho and lo unless otherwise specified. boldface limits apply over the operating junction temperature range, -40c to +125c . (continued) parameters symbol test conditions t j = +25c t j = -40c to +125c units min typ max min (note 12) max (note 12)
hip2103, hip2104 7 fn8276.0 november 27, 2013 undervoltage lockout (note 13) v dd falling threshold v uvf4 4v option 4.2 3.98 4.36 v v dd threshold hysteresis v uvh 0.34 0.267 0.37 v boot fet on resistance r don i vdd-hb = 75ma, hi = 0, li = 1 8.2 2.42 15 ? lo gate driver sinking r ds(on) rds lol i lo = 100ma, li = 0 2.68 0.61 11 ? sourcing r ds(on) rds loh i lo = -75ma, hi = 1 6.47 2.3 15 ? peak pull-up current i loh12 hi = 1 v dd = 12v, cload = 1000pf 1a i loh5 hi = 1 v dd = 5v, cload = 1000pf (hip2103 only) a peak pull-down current i lol12 hi = 0 v dd = 12v, cload = 1000pf 2a i lol5 hi = 0 v dd = 5v, cload = 1000pf (hip2103 only) a ho gate driver sinking r ds(on) rds hol i ho = 100ma, hi = 0 6.1 4.4 11 ? sourcing r ds(on) rds hoh i ho = -100ma, hi = 1 11.9 9.7 15 ? peak pull-up current i hoh12 hi = 1 v dd = 12v, cload = 1000pf 1a i hoh5 hi = 1 v dd = 5v, cload = 1000pf (hip2103 only) 1a peak pull-down current i hol12 hi = 0 v dd = 12v, cload = 1000pf 2a i hol5 hi = 0 v dd = 5v, cload = 1000pf (hip2103 only) a notes: 12. parameters with min and/or ma x limits are 100% tested at +25c, unless otherw ise specified. temperatur e limits established b y characterization and are not production tested. 13. the uv lockout does not disable the v dd and v cc outputs. dc electrical specifications v dd = v hb = 12v (for hip2103), v ss = v hs = 0v, v bat = 18v (for hip2104), li = hi = 0v. no load on ho and lo unless otherwise specified. boldface limits apply over the operating junction temperature range, -40c to +125c . (continued) parameters symbol test conditions t j = +25c t j = -40c to +125c units min typ max min (note 12) max (note 12)
hip2103, hip2104 8 fn8276.0 november 27, 2013 ac electrical specifications v dd = 12v, gnd = 0v, no load on outa or outb, unless otherwise specified. v dd load = 1f and v cc load = 1f (hip2104 only) boldface limits apply over the operating ju nction temperature range, -40c to +125c. parameters symbol test conditions t j = +25c t j = -40c to +125c units min typ max min max vden and vcen turn-on delay (figure 5) (hip2104 only) t den t cen vden = vcen = 1, v cc = v dd = 10%, v bat = 50v 1.69 1.0 2.5 ms vden and vcen turn-on delay (figure 5) (hip2104 only) t den t cen vden = vcen = 1, v cc = v dd = 10%, v bat = 18v 1.68 1.1 2.54 ms vden and vcen turn-on delay matching (figure 5) (vden - vcen) (hip2104 only) t venm vden = vcen = 1, v cc = 10%, v dd = 10% v bat = 50v 40 -290 340 ns vden and vcen turn-on delay matching (figure 5) (vden - vcen) (hip2104 only) t venm vden = vcen = 1, v cc = 10%, v dd = 10% v bat = 18v 40 -290 350 ns lo turn-off propagation delay (li to lo falling) (figure 6) t fl12 hi = 0, li = 1 to 0 v dd = 12v 27 13 39 ns t fl5 hi = 0, li = 1 to 0 v dd = 5v (hip2103 only) 30 23 46 ns ho turn-off propagation delay (hi to ho falling) (figure 6) t fh12 li = 0, hi = 1 to 0 v dd = 12v 23 10 35 ns t fh5 li = 0, hi = 1 to 0 vv = 5v (hip2103 only) 27 19 38 ns lo turn-on propagation delay (li to lo rising) (figure 6) t rl12 hi = 0, li = 0 to 1 v dd = 12v 21 732 ns t rl5 hi = 0, li = 0 to 1 v dd = 5v (hip2103 only) 25 12 37 ns ho turn-on propagation delay (hi to ho rising) (figure 6) t rh12 li = 0, hi = 0 to 1 v dd = 12v 23 935 ns t rh5 li = 0, hi = 0 to 1 v dd = 5v (hip2103 only) 28 15 40 ns turn-on/off propagation mismatch (ho rising to lo falling) (figure 6) t monhl li = 1 -> 0 hi = 0 -> 1 -2.5 -8 +3 ns turn-on/off propagation mismatch (lo rising to ho falling) (figure 6) t monlh hi = 1 -> 0 li = 0 -> 1 -4.2 -9.0 +5.4 ns lo output rise time (10% to 90% ) t r12 cl = 1nf v dd = 12v 20.5 735 ns t r5 cl = 1nf v dd = 5v (hip2103 only) 19.5 632 ns ho output rise time (10% to 90%) t r12 cl = 1nf v dd = 12v 21 835 ns t r5 cl = 1nf v dd = 5v (hip2103 only) 21 834 ns lo output fall time (90% to 10%) t f12 cl = 1nf v dd = 12v 17 330 ns t f5 cl = 1nf v dd = 5v (hip2103 only) 17 330 ns ho output fall time (90% to 10%) t f12 cl = 1nf v dd = 12v 16 230 ns t f5 cl = 1nf v dd = 5v (hip2103 only) 16 1.5 29 ns
hip2103, hip2104 9 fn8276.0 november 27, 2013 time delay to set sleep mode (note 14, figure 4) t slps hi = li = 0 -> 1 17 927 s time delay to reset sleep mode (note 14, figure 4) t slpr hi = 0, li = 0 -> 1 17 927 s note: 14. when hi and li are on simultaneously, ho and lo are never on simultaneously. this feature is intended to initiate sleep. thi s feature cannot be used to prevent shoot-through for normal alternating switching between li and hi. dead time must be provided when hi = 0 -> li = 1, or li = 0 -> hi = 1. see timing diagrams (figure 4). ac electrical specifications v dd = 12v, gnd = 0v, no load on outa or outb, unless otherwise specified. v dd load = 1f and v cc load = 1f (hip2104 only) boldface limits apply over the operating ju nction temperature range, -40c to +125c. (continued) parameters symbol test conditions t j = +25c t j = -40c to +125c units min typ max min max timing diagrams figure 3. vdd power-on/off timing for sleep mode 2m to hs 2m to hs 100 to ls 100 to ls ho = logic inputs lo = logic inputs ~ ~ ~ ~ ~ ~ ~ ~ uv threshold ho lo *sleep uvlo vdd vden vcc vcen ho lo *sleep uvlo vdd vden vcc vcen ~ ~ ~ ~ t vcen t vden t slps t slpr (vden and vcen apply to hip2104 only) *sleep is an internal state. minimal idd or ibat current results when active (high).
hip2103, hip2104 10 fn8276.0 november 27, 2013 figure 4. sleep mode enabled or cleared by hi and li inputs figure 5. vcen and vden delay matching figure 6. propagation delays timing diagrams (continued) 2m to hs 100 to ls dead time provided by controller ~ ~ ~ ~ ho lo sleep* hi li ho lo sleep* hi li ~ ~ 20s ~ ~ 20s * sleep mode is enabled when hi=li=1 for 20usecs. sleep mode is cleared when hi=0 and li = 1 for 20usecs. vcc vden vcen vdd vcc vden vcen t vcen vdd t vden 10% v cc 10% v dd t venm lo li lo li t rl t fl ho hi ho hi t rh t fh t monhl t monlh
hip2103, hip2104 11 fn8276.0 november 27, 2013 typical performance curves figure 7. v dd dropout vs v bat (hip2104 only) figure 8. v cc dropout vs v bat (hip2104 only) figure 9. hip2104 shutdown current (vcen = vden = 0, hs = v bat ) figure 10. hip2104 quiescent i bat (vcen = vden = li = hi = 1) figure 11. hip2104 v dd operating current limit figure 12. hip2104 v cc current limit 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 16 18 20 v d d ( o u t p u t ) no load 160 ? (75ma @ 12v) 2 3 4 vcc (output) 0 1 6 4321 v bat (input) 5 no load 44 ? (75ma @ 3.3v) 3.5 4.0 4.5 5.0 5.5 i bat (a) 2.0 2.5 3.0 10 20 30 40 50 v bat (vdc) 250 260 265 270 275 i bat (a) 235 240 10 20 30 40 50 v bat (vdc) 255 245 0 100 200 300 400 500 600 700 800 900 0 102030405060 i b a t ( a ) v bat (vdc) 0khz, +25c i bat , 10khz i bat , 20k 0 1 2 3 4 0 25 50 75 100 125 150 v cc (vdc) i cc (ma)
hip2103, hip2104 12 fn8276.0 november 27, 2013 figure 13. hip2104 v dd current limit, 0khz figure 14. hip2103 sleep current (hi = li = 1) figure 15. hip2103 operating current figure 16. hip2103, hip2104 undervoltage lockout figure 17. boot fet resistance fi gure 18. ho output resistance typical performance curves (continued) 0 2 4 6 8 10 12 14 0 50 100 150 v dd (vdc) i dd (ma) 1 2 3 4 5 6 7 8 9 10 5 6 7 8 9 1011121314 i b a t ( a ) v bat (vdc) 300 600 700 800 900 i dd (a) 0 100 57 9 13 15 v dd (vdc) 500 200 400 11 i bat , 0khz i bat , 10khz i bat , 20khz 3.5 3.7 3.9 4.1 4.3 4.5 -40 -20 0 20 40 60 80 100 120 uvlo (ho and lo) (v) temperature (c) 140 -40 -20 0 20 40 60 80 100 120 temperature (c) 140 0 2 4 6 8 10 12 14 16 18 20 ohms -40 -20 0 20 40 60 80 100 120 140 temperature (c) ohms 0 1 2 3 4 5 6 7 8 9 sourcing sinking
hip2103, hip2104 13 fn8276.0 november 27, 2013 functional description the following functional descri ption references the ?block diagram? on page 2. overview the hip2103 has independent control inputs, li and hi, for each output, lo and ho. there is no logic inversion for these input/output pairs. to minimize the possibility of shoot-through failures of the bridge fets caused by improper li and hi signals from an external controller, internal logic in the driver prevents both outputs being high simultan eously. when either input is high, the high input must go low before a high on the other input propagates to its respective drive output. if both inputs are high simultaneously, both output are low. if one input is high, followed by the other input going high, th e internal logic prevents any shoot through. note that the internal logic does not prevent shoot-through if the dead-time prov ided by the external controller is not sufficiently long as requir ed by the turn-on/off times of the bridge fets. if both inputs are high simultaneously for longer than 30s, the driver initiates a sleep mode to reduce the bias current to minimize the battery drain. when in sleep mode, the ho output is in a high-impedance state (2m ? between ho and hs) and the lo output is held low with an active 100 ? pull-down resistor. the 100 ? pull-down prevents inadvertent shoot-through resulting from transients on the bridge voltage while both drivers are in the sleep mode. the undervoltage lockout (uvlo) on v dd drives ho and lo low when vdd is less that the uv threshold. sleep mode is initiated if uvlo is asserted for longer than 30s. the high-side driver bias is established by the boot capacitor connected between hb and hs. the charge on the boot capacitor is provided by the internal boot fet that is connected between vdd and hb. the current path to charge the boot cap is enabled (boot fet is on) when the drain voltage on the low-side bridge fet (vho) is <1v and when ho = 0. when the boot fet is on, the boot cap is charged to approximately v dd . the boot fet turns off when h0 = 1. the boot capacitor provides the charge necessary to turn on the fet and maintains the bias voltage on the high side driver fo r the duration of the period while the fet is on. see the following for details on selecting the boot capacitor value. the peak charge current is limited in amplitude by the inherent resistance of the boot fet and by the delta voltage between v dd and the drain-source voltage of the low-side bridge fet (v hs ) less the boot cap voltage. assuming that the on time of the low-side fet is sufficiently long to fully charge the boot capacitor, the boot voltage charges very close to v dd (less the voltage across the drain-source of the lo w-side bridge fet). when the hi input transitions high, the high-side bridge fet is driven on. because the hs node is connected to the source of the high-side fet, the hs node rises al most to the level of the bridge voltage, v bat (less the conduction voltage across the bridge fet). because the boot capacitor voltage is referenced to the source voltage of the high-side fet, the hb node is v dd volts above the hs node. simultaneously with hi = 1, the boot fet is turned off preventing the boot capacitor from discharging back to vdd. because the high-side driver circuit is referenced to the hs node, the ho output is now approximately v hb + v bat above ground. during the low to high transition of the phase node (hs), the boot capacitor sources the necessary gate charge to fully enhance the high-side bridge fet gate. after the gate of the bridge fet is fully charged, the boot capacitor no longer sources charge to the gate but continues to provide bias current to the high-side driver through out the period while the high-side bride fet is on. to prevent the voltage on the boot capacitor from drooping excessively, the boot capacitor valu e must be sized appropriately. if the boot voltage droops to the uvlo threshold, the high-side fet is turned off to prevent damage due to insufficient gate voltage. figure 19. lo output resistance typical performance curves (continued) -40 -20 0 20 40 60 80 100 120 140 temperature (c) ohms 0 1 2 3 4 5 6 7 8 9 sourcing sinking
hip2103, hip2104 14 fn8276.0 november 27, 2013 selecting the boot capacitor value the boot capacitor value is chosen not only to supply the internal bias current of the high-side driver but also, and more significantly, to provide the gate charge of the driven fet without causing the boot voltage to sag excessively. in practice, the boot capacitor should have a total charge that is about 20 times the gate charge of the driven power fet for approximately a 5% drop in voltage after charge has been transferred from the boot capacitor to the gate capacitance. the following parameters are required to calculate the value of the boot capacitor for a specific amount of voltage droop when using the hip2103, hip2104. in the following example, some values used are specific to the hip2103, hip2104 and others are arbitrary. the values should be changed to comply with the actual application. the following equations calculates the total charge required for the period: qc = qg40_12v + period x (ihb + vho/rgs + igate_leak) cboot = qc/(ripple * v dd ) cboot = 0.324f if the gate to source resistor is removed (rgs is usually not needed or recommended), then: cboot = 0.124f v dd = 12v this is the nominal value of vdd for the hip2104 vhb = v dd = vho high side driver bias voltage referenced to vhs period = 100s this is the longest expected switching period ihb = i hbs20k + i hb20k = 295a high side driver bias current at 20khz rgs = 10k ? gate-source resistor ripple = 5% desired ripple voltage on the boot cap igate_leak = 100na gate leakage current (from vendor datasheet) qg40_12v = 45nc from figure 20 figure 20. typical mosfet gate charge vs gate voltage 4 2 0 6 8 10 12 14 16 0 5 10 15 20 25 30 35 45 50 60 qg, gate charge (nc) vgs, gate voltage vds = 40v vds = 80v typical applications figure 21. half bridge motor drive topology ucontroller hip2104 vbat vcen vcc vdd hi li e p a d lo hs ho hb vden vss dc motor v batt 50vmax v batt
hip2103, hip2104 15 fn8276.0 november 27, 2013 figure 22. full bridge motor driver topology typical applications ucontroller hip2104 vbat vcen vcc vdd hi li epad lo hs ho hb vden vss dc motor hi li lo hs ho hb vss hip2103 epad vdd vdd v batt v batt vdd
hip2103, hip2104 16 fn8276.0 november 27, 2013 application examples above are examples (figures 21, 22, and 23) of how the hip2103, hip2104 can be configured for various motor drive application with the hip2104 supplying the 12v bias for the other hip2103s and the v cc (3.3v) bias for the controlle r. vcen and vden are used to turn on and off the internal linear regulators of the hip2104. because of entire switching of the bias supplies is implemented with logic, a signal switch, instead of a power switch, can be used to turn on and off the driver and controller. a switch debouncing delay of 1ms is provid ed on vden and vcen. the external diode on vbatt is used to hold up the voltage on the v bat input in the presence of severe ripple as usually seen on li-on batteries. in the case of the hip2104, when vden is low, the driver sections enters the sleep mode. when vcen is low, the bias to the controller is removed resulting with the lowest possible idle current in both the controller and the driver minimizing the drain on the battery when the motor drive is off. sleep mode can also be initiated on the hip2104 by driving hi and li high simultaneously. in this case , the sleep mode current is substantially higher (~250a) because the v dd and v cc outputs are still active. in the case of the hip2103, sleep mode in the driver is initiated when hi and li are both high simultaneously as previously described. if vdd is provided by an accompanying hip2104, turning off the vdd output of the hip2104 will also result with virtually no sleep current in the hip2103 because there is no bias. for example, in the bldc configuration, the sleep mode current will be ~5a (in the hip2104) and no current in both of the hip2103s. transients on the hs node an important operating condition th at is frequently overlooked is the transient on the hs pin that occurs when the bridge fets turn on or off. the absolute maximum negative transient (see page 5) allowed on the hs pin is -10v without any time restrictions on the duration of the transient. in most well designed pcbs, all that will be required is that the transi ent be less negative than -10v. figure 23. bldc (3-phase) motor drive topology typical applications ucontroller hip2104 vbat vcen vcc vdd hi li epad lo hs ho hb vden vss v batt hi li lo hs ho hb vss hip2103 epad vdd vdd hi li lo hs ho hb vss hip2103 epad vdd bldc motor v batt
hip2103, hip2104 17 fn8276.0 november 27, 2013 the negative transient on the hs pi n is the result of the parasitic inductance of the low-side drain-source conductor path on the pcb. even the parasitic inductance of the low-side fet body contributes to this transient. when the high-side bridge fet turns off (see figure 24), as a consequence of the inductive characteristics of a motor load, the current that was flowing in the high-side fet (blue) must ra pidly commutate through the low side fet (red). the amplitude of the negative transient impressed on the hs node is (l x di/dt) where l is the total parasitic inductance of the low-side fet drain-source path and di/dt is the rate at which the high-side fet is turned off. with the increasing current levels of new generation motor drives, appropriately clamping of this transient be comes more significant for the proper operation of bridge drivers. fortunately, the hip2103, hip2104 can withstand greater amplitudes of negative transients than what is availabl e in many other bridge drivers. the maximum negative voltage on the hs pin is rated for -10v with no time during limit. another component of negative voltage is from the body diode of the low side fet during the dead time. when current is flowing from source to drain, the cond uction voltage is approximately 1 to 1.5v negative impressed on the hs pin (possibly greater during fault load conditions). because the hip2103, hip2104 is rated for -10v without any time constraints, this negative voltage component is of no consequence. in the unlikely event that the negative transient exceeds -10v, there are several ways of reducing the negative amplitude of this transient if necessary. if the bridge fets are turned off more slowly to reduce di/dt, the amplitude will be reduced but at the expense of more switching losses in the fets. careful pcb design will also reduce the value of the parasitic inductance. however, in extreme cases, these two solutions by themselves may not be sufficient. figure 25 illustrates a simple method for clamping the negative transient. two series co nnected, fast 1 amp pn junction diodes are connected between hs and vss as shown. it is important that these diodes be placed as close as possible to the hs and vss pins to minimize the parasitic inductance of this current path between the two pins. two diodes in series are required because they are in parallel with the body diode of the low side fet. if only one diode is used for the clamp, it will conduct some of the negative load current that is flowing in the body diode of the low side fet. an alternative to the two series connected diodes is one diode and a resistor (figure 26). in this case, it is necessary to limit the current in the diode with a small value resistor, r hs , connected between the phase node of the 1/2 bridge and the hs pin. observe that r hs is effectively in series with the ho output and serves as a peak current limi ting gate resistor on ho. the value of r hs is determined by how much average current in the clamping diode is acceptable. current in the low side fet flows through the body diode during the dead time resulting with a negative voltage on hs that is typically about -1.5v. when the low-side fet is turned on, the cu rrent through the body diode is shunted away into the channel and the conduction voltage from source to drain is typically much less than the conduction voltage through the body diode. consequently, significant current will flow in the clamping diode only during the dead time. because the dead time is much less than th e on time of the low side fet, the resulting average current in the clamping diode is very low. the value of r hs is then chosen to limit the peak current in the clamping diode and usually just a few ohms is necessary. the methods to clamp the negative transients with diodes can still result with high frequenc y oscillations on the hs node depending on the parasitics of the pcb design. an alternative to the clamping diode in figure 26 is a small value capacitor instead of the diode. this capacitor and r hs is very effective for minimizing the negative spike amplitude and oscillations. figure 24. parasitic in ductance on hs node vss hs lo ho inductive load + - + - hb c boot figure 25. two clamping diod es to suppress negative transients figure 26. resistor and diod e negative transient clamp vss hs lo ho inductive load hb c boot 1v - + vss hs lo ho inductive load + - + - r hs hb c boot
hip2103, hip2104 18 fn8276.0 november 27, 2013 but this solution also has its li mitations. depending on the value of the filter capacitor and the pwm switching frequency, r hs may dissipate significant power because the voltage on the capacitor is switching between the bridge voltage and ground. usually, the power dissipated by r hs is small because the switching frequency for most mo tor drives is <20khz and the value used for c filter is typically about 1000pf. another issue is that the charge on c filter will be partially transferred to the gate of the high-side fet when the low-side fet turns on. when the phase node go es low, a voltage is impressed across r hs as shown in figure 27. because ho is low, the voltage across r hs is also across the gate of the high side fet. if the filter cap is very large, the voltage on the gate will approach the bridge voltage turning on the high-side fet resulting with shoot-through. fortunately, the voltage across r hs is much less than the bridge voltage for two reasons. first, the voltage across r hs is determined by the turn-on time of the low side fet. as the low-side fet is turning on, the charge on the filter cap is depleting lessening the voltage across r hs . also, because the relatively large gate capacitance of the high-side fet is in parallel with r hs, the voltage impressed on the gate is further reduced. in a practical application using value of c filter = 4700pf and r hs =1 ? , the voltage impressed on the bridge fet is less than 1v. the emphasis of suppressing tran sients on the hs pin has been with negative transients. please note that a similar transients with a positive polarity occurs when the low-side fet turns off. this is usually not a problem unless the bridge voltage is close to the maximum rated operating voltage of 50v. note that the maximum voltage ratings for the hs and hb nodes also must be observed when the posi tive transient occurs. the maximum rating for (vhb - vhs) must also not be overlooked. when a negative transient, vneg, is present on the hs pin, the voltage differential across hb and hs will approach vdd + vneg. if the transient dura tion is short compared to the charging time constant of the bo ot diode and boot capacitor, the voltage across hb and hs is not significantly affected. however, another source of negative voltage on the hs pin will more likely increase the boot capacitor voltage. while current is flowing from the source to drain of the low-si de fet during the dead time, the current flows through body diode of the fet. depending on the size of the fet and the amplitude of the reverse current, the voltage across the diode can be as high as -1.5v and much higher during a load fault. because this negative voltage has little impedance, the boot capacitor can charge to a voltage greater than vdd (for example vdd + 1.5v). it may be necessary to either clamp the voltage as described in figures 25 through 27 and/or keep the dead time as short as possible. general pcb layout guidelines the ac performance of the hip2103, hip2104 depends significantly on the design of th e pc board. the following layout design guidelines are recommended to achieve optimum performance: ? place the driver as close as possible to the driven power fet. ? understand where the switching power currents flow. the high amplitude di/dt currents of the driven power fet will induce significant voltage transients on the associated traces. ? keep power loops as short as possible by paralleling the source and return traces. ? use planes where practical; they are usually more effective than parallel traces. ? avoid paralleling high amplitude di/dt traces with low level signal lines. high di/dt will in duce currents and consequently, noise voltages in the low level signal lines. ? when practical, minimize impedances in low level signal circuits. noise, magnetically induced on a 10k ? resistor, is 10x larger than the noise on a 1k ? resistor. ? be aware of magnetic fields emanating from motors and inductors. gaps in the magnetic cores of these structures are especially bad for emitting flux. ? if you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines to minimize coupling. ? the use of low inductance components such as chip resistors and chip capacitors is highly recommended. ? use decoupling capacitors to reduce the influence of parasitic inductance in the v bat , v dd and gnd leads. to be effective, these caps must also have the shortest possible conduction paths. if vias are used, connect several paralleled vias to reduce the inductance of the vias. ? it may be necessary to add resi stance to dampen resonating parasitic circuits especially on lo and lo. if an external gate resistor is unacceptable, then th e layout must be improved to minimize lead inductance. ? keep high dv/dt nodes away from low level circuits. guard banding can be used to shunt away dv/dt injected currents from sensitive circuits. ? avoid having a signal ground plane under a high amplitude dv/dt circuit. the parasitic capa citance of a ground plane, cp, relative to the high amplitude dv/dt circuit will result in injected (cp x dv/dt) currents into the signal ground paths where c is the parasitic capa citance of the ground plane. ? do power dissipation and voltage drop calculations of the power traces. many pcb/cad programs have built in tools for calculation of trace resistance. the internet is also a good source for resistance calculat ors for pcb trace resistance. figure 27. resistor and capacitor negative transient filter vss hs lo ho inductive load r hs hb c boot + _ c filter i bat , 0khz
hip2103, hip2104 19 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8276.0 november 27, 2013 for additional products, see www.intersil.com/en/products.html ? large power components (power fets, electrolytic caps, power resistors, etc.) have internal parasitic inductance which cannot be eliminated. this must be accounted for in the pcb layout and circuit design. ? if you simulate your circuits, consider including parasitic components especially parasitic inductance. general epad heatsinking considerations the epad of the hip2103, hip2104 is electrically connected to vss through the ic substrate. the epad has two main functions: to provide a quiet signal ground and to provide heat sinking for the ic. the epad must be connected to a ground plane and switching currents from the driven fets should not pass through the ground plane under the ic. figure 28 is a pcb layout example of how to use vias to remove heat from the ic through the epad. for maximum heatsinking, it is recommended that a ground plane, connected to the epad, be added to both sides of the pcb. a via array, within the area of the epad, will conduct heat from the epad to the gnd plane on the bottom layer. the number of vias and the size of the gnd planes required for adequate heatsinking is determined by the power dissipated by the hip2103, hip2104, the air flow, and the maximum temperature of the air around the ic. note that a separate plane is added under the high side drive circuits and is connected to hs. in a manner similar to the ground plane, the hs plane provides the lowest possible parasitic inductance for the ho/hs gate drive current loop. see an1899 ?hip2103, hip2104 3-phase, full, or half bridge motor driver? for an example of pcb layout of a real application. about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability vdd epad gnd plane component layer hi li ls hb ho hs lo epad gnd plane bottom layer vdd hi li ls hb ho hs lo this plane is connected to hs and is under all high side driver circuits figure 28. typical pcb pattern for thermal vias revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change november 27, 2013 fn8276.0 initial release
hip2103, hip2104 20 fn8276.0 november 27, 2013 package outline drawing l8.3x3a 8 lead thin dual flat no-lead plastic package rev 4, 2/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.20mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing co nform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 6x 0.65 1.50 0.10 8 1 8x 0.30 0.10 6 0.75 0.05 see detail "x" 0.08 0.10 c c c ( 2.90 ) (1.50) ( 8 x 0.30) ( 8x 0.50) ( 2.30) ( 1.95) 2.30 0.10 0.10 8x 0.30 0.05 a mc b 4 2x 1.950 (6x 0.65) index area pin 1 compliant to jedec mo-229 weec-2 except for the foot length. 7.
hip2103, hip2104 21 fn8276.0 november 27, 2013 package outline drawing l12.4x4a 12 lead dual flat no-lead plastic package rev 2, 6/12 typical recommended land pattern detail "x" side view top view bottom view located within the zone indicated . the pin #1 identifier may be unless otherwise specified, to lerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. lead width applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 4.00 1.58 0.15 ( 3.75) (4x) ( 12x 0 . 25) ( 10x 0 . 5 ) 1.00 max base plane c seating plane 0.08 c 0.10 c 12 x 0.25 see detail "x" 0.10 4 ca mb index area 6 pin 1 4.00 a b pin #1 index area 2.5 ref 10x 0.50 bsc 6 ( 12 x 0.65 ) 0 . 00 min. 0 . 05 max. c 0 . 2 ref 12x 0 . 45 2.80 ( 1.58) ( 2.80 ) 0.05 m c 7 6 12 1

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